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e preliminary december 1998 order number: 290581-005 n low-cost linear flash card n miniature card specification compliant n single supply smartvoltage operation ? 5 v or 3.3 v read/write n fast read performance ? 100 ns max access time at 5 v ? 150 ns max access time at 3.3 v n x16 data interface n high-performance random writes ? 8 m s typical word write at 5 v ? 17 m s typical word write at 3.3 v n 50 m a maximum deep power-down at 4 mb n automated write and erase algorithms ? 28f008sc/28f016sc commands n enhanced automated suspend options ? write suspend to read ? block erase suspend to write ? block erase suspend to read n enhanced data protection features ? flexible block locking ? user write protect switch n etox ? v nonvolatile flash technology n 100,000 erase cycles per block n 64-kword blocks intel ? series 100 flash memory miniature card offers a small form factor, low cost, removable solid-state storage solution for consumer applications. some of these applications include digital audio recorders, digital cameras, wireless communications, and hand-held pcs. manufactured with intel ? flashfile? memory, this card takes advantage of a revolutionary architecture that provides innovative capabilities, automated write/erase algorithms, reliable operation and very high read/write performance. note: this document formerly known as series 100 flash memory miniature card . 3/5 volt series 100 flash memory miniature card ifm002a, ifm004a, IFM008A
information in this document is provided in connection with intel products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liability or warranties relating to fitness for a particular purpose, merchantabili ty, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. the ifm002a, ifm004a, IFM008A may contain design defects or errors known as errata which may cause the product to deviate from published specifications. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are referenced in this document, or other intel literature, may be obtained from: intel corporation p.o. box 5937 denver, co 80217-9808 or call 1-800-879-4683 or visit intels website at http://www.intel.com copyright ? intel corporation 1997, 1998 cg-041493 *third-part y brands and names are the propert y of their respective owners
e ifm002/004/008a 3 preliminary contents page page 1.0 scope of document ................................ 5 2.0 product overview .................................. 5 3.0 series 100 miniature card architecture overview ....................... 5 3.1 card pinout and signal description ............. 5 4.0 memory control logic ......................... 8 4.1 bus operations............................................ 8 4.1.1 read array............................................ 8 4.1.2 output disable ...................................... 8 4.1.3 standby ................................................ 8 4.1.4 deep power-down................................ 9 4.1.5 read identifier codes operation........... 9 4.1.6 cui writes ............................................ 9 4.2 smartvoltage technology.......................... 10 5.0 card control logic ............................. 10 5.1 word addressing ....................................... 10 5.2 decode logic............................................. 10 5.3 write protect switch .................................. 10 5.4 data control .............................................. 10 6.0 command definitions............................ 12 6.1 read array command ............................... 12 6.2 read identifier codes command............... 13 6.3 read status register command ............... 13 6.4 clear status register command ............... 13 6.5 block erase command .............................. 13 6.6 word write command ............................... 14 6.7 block erase suspend command ............... 14 6.8 word write suspend command ................ 14 6.9 set block lock-bit command .................... 15 6.10 clear block lock-bits command ............. 15 7.0 card attribute information ............. 16 7.1 card information structure......................... 17 7.2 attribute information structure ................... 17 7.3 card attribute information data.................. 18 8.0 system design considerations ........ 21 8.1 power supply decoupling .......................... 21 8.2 power-up/down protection........................ 21 8.3 busy# and byte write/block erase polling22 8.4 v cc , reset# transitions and the command/status registers ...................... 22 8.5 preformatted for ftl.................................. 22 9.0 electrical specifications ................. 23 9.1 absolute maximum ratings ....................... 23 9.2 operating conditions ................................. 23 9.3 capacitance............................................... 23 9.4 dc characteristics ..................................... 24 9.5 ac characteristics ..................................... 26 9.5.1 read operations ................................. 26 9.5.2 write operations ................................. 27 9.5.3 power-up timing ................................ 28 9.6 erase and data write performance ........... 29 10.0 packaging............................................... 30 11.0 ordering information ....................... 31 12.0 additional information..................... 31 related intel information.................................. 31
ifm002/004/008a e 4 preliminary revision history number item -001 original version -002 added section 8.5, preformatted for ftl modified test conditions for v ol modified test conditions for v oh modified vcc standby current for 4 mbyte cards added jedec id tuple to the cis corrected references to byte writes as word writes -003 altered specification throughout document for addition of the IFM008A 8-mbyte card following figure 3, device identifier code memory map, added note for clarification in section 6.4, clear status register command, reworded the note to correspond to the wsm diagrams in the 28f008sc and 28f016sc memory device specifications in section 6.9, set block lock-bit command, removed reference to device address in section 9.1, absolute maximum ratings, combined v cc supply voltage and voltage on any pin (except v cc ) specifications into new specification voltage on any pin; changed note 2 accordingly in section 9.2.1, capacitance, combined c in and c out specifications for individual cards into one general c in and c out specification for all cards in section 9.2.2, ac input/output test conditions, added note to clarify figure 5 in section 9.3, dc characteristics, changed specified values for: i li , i lo , i ccs, i ccd in section 9.3, dc characteristics, added ma for units of i ccr in section 9.3, dc characteristics, removed notes 7 and 8 in section 9.3, dc characteristics, changed maximum v ih value at v cc = 5 v from 0.7 v cc to v cc + 0.5 in section 9.4.1, read operations, changed specified value for oe# access time 5 v max from 40 ns to 50 ns in appendix b updated document references listed in table related intel information re-worded the following areas of the document for clarity: pin description of signals a0- a24 in table 3 pin description of signal reset# in table 3 section 4.1.1, read array section 6.6, word write command section 6.8, word write suspend command section 8.4, v cc , reset# transitions and the command/status registers corrected minor clerical errors in document -004 revised maximum deep power-down highlight on cover sheet updated disclaimer information changed layout of section 9.0, electrical specifications -005 changed name of document from series 100 flash memory miniature card
e ifm002/004/008a 5 preliminary 1.0 scope of document this datasheet provides a card architecture overview, ac and dc characteristics and command definitions. 2.0 product overview the 4- and 8-mbyte flash memory cards each contain a flash memory array that consists of two or four 28f016sc (2-mbyte) tsop memory devices, respectively. each 28f016sc contains 32 distinct, individually-erasable, 64-kbyte blocks. therefore, the 4- and 8-mbyte cards contain 64 and 128 independently-erasable blocks. the 2-mbyte flash memory cards contain a flash memory array that consists of two 28f008sc (1-mbyte) tsop memory devices. each 28f008sc contains 16 distinct, individually- erasable, 64-kbyte blocks. therefore, the 2-mbyte cards contain 32 independently-erasable blocks. at the device level, internal algorithm automation allows execution of write and erase operations using a two-write command sequence in the same way as the flash memory in the series 2 or value series 100 cards. the automated write/erase algorithms ensure that data is reliably written in the least amount of time. 3.0 series 100 miniature card architecture overview the series 100 miniature card is a simple array of flash devices in a miniature card form factor. this card offers a low-cost, small form factor, removable memory solution at 2-, 4- and 8-mbyte densities. two 28f008sc or 28f016sc devices in parallel provide the lower and upper bytes for a 16-bit access. the attribute information structure (ais) for the series 100 miniature card is stored in block 0 of the flash memory to reduce the attribute memory cost overhead of an eeprom or asic. 3.1 card pinout and signal description the miniature card specification provides the system interface for the series 100 miniature card. the detailed specifications for this interface are described in the miniature card specification. a[20:0] oe# we# rp# ce# a[20:0] oe# we# rp# ce# ce# ce# d[15:8] we# oe# a[20:0] d[7:0] a21 cel# ceh# busy# a[20:0] oe# we# rp# a[20:0] oe# we# rp# decoder d[7:0] d[7:0] d[7:0] d[7:0] ry/by# ry/by# ry/by# ry/by# 2 2 4 reset# 28f016sc 28f016sc 28f016sc 28f016sc and decoder 0581_01 figure 1. 8-mbyte flash memory card block diagram showing major functional elements
ifm002/004/008a e 6 preliminary table 1. series 100 miniature card interface signals pad # signal name pad # signal name pad # signal name 1a 18 21 d 12 41 a 4 2a 16 22 d 10 42 cel# 3a 14 23 d 9 43 a 1 4v ccr (1) 24 d 0 44 casl# (1) 5 ceh# 25 d 2 45 cash# (1) 6a 11 26 d 4 46 cd# 7a 9 27 rfu 47 a 21 (4) 8a 8 28 d 7 48 busy# 9a 6 29 sda (1) 49 we# 10 a 5 30 scl (1) 50 d 14 11 a 3 31 a 19 51 rfu (1,2) 12 a 2 32 a 17 52 d 11 13 a 0 33 a 15 53 vs2# (1) 14 ras# (1) 34 a 13 54 d 8 15 a 24 (1) 35 a 12 55 d 1 16 a 23 (1) 36 reset# 56 d 3 17 a 22 (1) 37 a 10 57 d 5 18 oe# 38 vs1# 58 d 6 19 d 15 39 a 7 59 rfu (1,2) 20 d 13 40 bs8# (1) 60 a 20 (3) notes: 1. these signals make no internal connection into the card. 2. reserved pins must not be driven by the host. they should be left floating. 3. a 20 is not decoded on the 2-mbyte card. 4. a 21 is only decoded on the 8-mbyte card. table 2. series 100 miniature card power/insertion signals signal # signal name 61 gnd 62 cins# 63 v cc
e ifm002/004/008a 7 preliminary table 3. series 100 miniature card interface signal description symbol type name and function a 0 Ca 24 input address inputs: addresses a 0 through a 24 enable direct addressing of up to 64 mb of memory on the card. however, the memory will wrap at the card density boundary. the system should not try to access memory beyond the cards density, since the upper addresses are not decoded. d 0 Cd 15 input/ output data input/output: d 0 through d 15 constitute the bi-directional data bus. d 15 is the most significant bit. cel#, ceh# input card enable low & high: cel# enables accesses on the low byte of the data bus d 0 C7 . ceh# enables accesses on the high byte of the data bus d 8C15 . both cel# and ceh# are active low signals. a 16-bit host must always assert both cel# and ceh#. oe# input output enable: active low signal, enables read data from the memory card. we# input write enable: active low signal, enables write data to the memory card. busy# output busy: active low signal, indicates the status of internally timed erase or write activities. a high output indicates the memory card is ready to accept another command. cd# output card detect: active low signal, provides for card insertion detection. cd# connects to ground internally on the memory card, and will be forced low when the cd# interface signal connects to the host. reset# input reset: active low input signal, resets each memory devices command user interface and places the card into a deep power-down mode. the host must drive this signal. vs1#, vs2# output voltage sense: notifies the host socket of the cards v cc requirements. vs 1 is grounded and vs 2 is left open to indicate a 3.3 v capable card has been inserted. rfu - reserved for future use table 4. series 100 miniature card power/insertion signal description symbol type name and function cins# output card insertion detect: this signal provides for early card insertion detection. cins# connects to ground internally on the memory card, and will be forced low when the power/insertion signals connect to the host. v cc - card power supply: 3.3 v or 5 v gnd - ground
ifm002/004/008a e 8 preliminary 60 59 30 29 vcc (63) cins# (62) gnd (61) 1 2 31 32 miniature card bottomside 0581_02 figure 2. card interface signal assignment 4.0 memory control logic 4.1 bus operations the host executes read, write and erase operations by issuing the appropriate command to the flash memory devices command user interface (cui). the cui, which supports the command sets of the cards 28f008sc or 28f016sc memory devices, serves as the interface between the host processor and internal operation of the flash devices. commands to the memory devices can be issued to the cui using standard microprocessor bus cycles. 4.1.1 read array the host enables reads from the card by writing the appropriate read command to the cui. the 28f008sc or 28f016sc memory devices auto- matically reset to read array mode upon initial card power-up or after card reset. cel#, ceh#, and oe# must be logically active to obtain 16 data bits at the outputs. the card enables (cel# and ceh#) are used to select the addressed devices. output enable (oe#) is the data input/output (d 0 Cd 15 ) direction control, and when active, drives data from the selected memory onto the data bus. we# must be driven to v ih (inactive) during a read access. 4.1.2 output disable with oe# at a logic-high level (v ih ), the device outputs are disabled. outputs (d 0 Cd 15 ) are placed in a high-impedance state. 4.1.3 standby cel# and ceh# at a logic-high level (v ih ) places the card in standby mode. standby operation disables much of the cards circuitry and substantially reduces device power consumption. the outputs (d 0 Cd 15 ) are placed in a high- impedance state independent of the status of oe#. if the host deselects the card during a write or erase, the card continues to function and consume normal active power until the operation completes.
e ifm002/004/008a 9 preliminary 4.1.4 deep power-down reset# at v il initiates the deep power-down mode. during reads, an active reset# deselects the memory, places output drivers in a high-impedance state, and turns off all internal circuits. reset# must be held low for a minimum of 100 ns. after returning from deep power-down, the host must wait before initial memory access outputs are valid, as determined by t phqv . after this wake-up interval, the host can resume normal operations to the card. card reset forces the cui to reset to read array mode and sets the status register to 80h. during block erase, byte write, or lock-bit configuration modes, an active reset# will abort the operation. busy# remains low until the reset operation completes. memory contents being altered are no longer valid; the data may be partially erased or written. the host must wait after reset# goes to logic-high (v ih ) before it can write another command, as determined by t phwl . it is important to assert reset# to the card during a system reset. w hen a host comes out of reset, it may require the ability to immediately execute code from the card. if a cpu reset occurs without a card reset, the host will not be able to read from the card if that card is in a different mode when the system reset occurs. for example, if an end-user initiates a host reset when the card is in read status register mode, the host will attempt to read code from the card, but will actually read status register data. intels series 100 miniature card allows proper card reset following a system reset thr ough the use of the reset# input. system reset# circuitry can reset the host cpu in addition to the card. 4.1.5 read identifier codes operation the read identifier codes operation outputs the manufacturer code, device code, and block lock configuration codes (for each block), see figure 3. using the manufacturer and device codes, the system cpu can automatically match the device with its proper algorithms. the block lock codes identify locked and unlocked blocks. (blocks 2 through 14) block 15 lock configuration code block 1 lock configuration code manufacturer code device code block 0 lock configuration code reserved for future implementation reserved for future implementation reserved for future implementation reserved for future implementation reserved for future implementation block 15 block 1 block 0 fffff f0004 f0003 f0002 f0001 f0000 1ffff 10004 10003 10002 10001 10000 0ffff 00004 00003 00002 00001 00000 0581_03 figure 3. device identifier code memory map 4.1.6 cui writes writes to the cui enable reading of device data and intelligent identifiers. they also control inspection and clearing of the status register. the contents of the interface register serves as input to the internal state machine on each component.
ifm002/004/008a e 10 preliminary the cui itself does not occupy an addressable memory location. the interface register is a latch used to store the command, address and data information needed to execute the command. erase setup and erase confirm commands require both appropriate command data and an address within the block to be erased. the write setup command requires both appropriate command data and the address of the location to be written, while the write command consists of the data to be written and the address of the location to be written. the cui is written by bringing we# to a logic-low level (v il ) while ce# is low. addresses and data are latched on the rising edge of we#. standard microprocessor write timings are used. when a write or erase command has been issued to the cui, the internal write state machine (wsm) becomes busy and will not be ready until it has completed the operation. 4.2 smartvoltage technology smartvoltage technology provides a choice of v cc at 3.3 v or 5.0 v. v cc at 3.3 v consumes approx- imately one-fourth the power of v cc at 5.0 v. however, v cc at 5.0 v provides the highest read performance. internal device detection circuitry automatically configures the device. 5.0 card control logic 5.1 word addressing the series 100 miniature card uses two x8 devices in parallel to form the miniature card x16 data bus (see figure 1). if the host writes a command to the card, it must make sure that it writes the command to both devices in the card. for example, a component write command is 40h, so a card write command must be 4040h. this same procedure must be followed when reading from the status register. a component status register is only 8 bits and may return 80h when read. however, the card status register is 16 bits and may return 8080h. 5.2 decode logic the decode logic enables the appropriate component device pair during a read or write access. unused upper addresses for the series 100 miniature card will not be decoded. the address decoding will wrap around at the cards density. 5.3 write protect switch the series 100 miniature card has a write protect switch on the side of the card. when the switch is in the write protect position, the card blocks all writes to the card (see figure 4). note when the write protect switch is in the write protect position all writes are disabled to the flash array including all commands to the cui. write protect position writeable position 0581_05 note: the write protect switch is represented by the solid black rectangle. figure 4. write protect switch 5.4 data control as shown in table 5, data paths and directions are selected by the data control logic using we#, oe#, cel#, and ceh# as logic inputs.
e ifm002/004/008a 11 preliminary table 5. data access mode truth table mode reset# cel# ceh# oe# we# a 0 d 8 C15 d 0C7 notes low byte-read v ih v il v ih v il v ih x high-z low (6) 1,2,3, high byte-read v ih v ih v il v il v ih x high (6) high-z 1,2,3, word-read v ih v il v il v il v ih x high (6) low (6) 1,2,3, low byte-write v ih v il v ih v ih v il x xxx low (6) 3,4, high byte-write v ih v ih v il v ih v il x high (6) xxx 3,4, word-write v ih v il v il v ih v il x high (6) low (6) 3,4, manufacturer id v ih v il v il v il v ih v il 89h 89h device id v ih v il v il v il v ih v ih a6h a6h 5 standby v ih v ih v ih x x x high-z high-z output disable v ih xxv ih v ih x high-z high-z power-down v il x x x x x high-z high-z notes: 1. refer to dc characteristics . 2. x can be v il or v ih for control signals and address. 3. busy# is v ol when the wsm is executing internal byte write or block erase algorithms. it is v oh when the wsm is not busy, in erase suspend mode, or deep power-down mode. 4. refer to table 6 for valid d in during a write operation. 5. the device code can be a6h, a7h or aah. software should check for all three cases for compatibility with future cards. 6. high indicates high byte data, low indicates low byte data.
ifm002/004/008a e 12 preliminary 6.0 command definitions device operations are selected by writing specific commands into the command user interface. table 6 defines the 28f008sc commands. note: when the write protect switch is in the write protect position all writes are disabled to the flash array including commands to the cui. 6.1 read array command upon initial device power-up and after exit from deep power-down mode, the card defaults to read array mode. the host can also read by writing the read array command. the device remains enabled for reads until the host writes another valid command. once the internal wsm has started a block erase, byte write or lock-bit configuration, the device will not recognize the read array command until the wsm completes its operation. however, the host can suspend the wsm using an erase suspend or byte write suspend command. table 6. command definitions (6) bus cycles first bus cycle second bus cycle command req'd. notes oper (1) addr (2) data (3) oper (1) addr (2) data (3) read array/reset 1 write x ffffh read identifier codes 3 2 4 write x 9090h read ia id read status register 2 write x 7070h read x srd clear status register 1 write x 5050h block erase 2 write ba 2020h write ba d0d0h word write 2 5 write wa 4040h or 1010h write wa wd block erase and byte write suspend 1 write x b0b0h block erase and byte write resume 1 write x d0d0h set block lock-bit 2 write ba 6060h write ba 0101h clear block lock-bits 2 write x 6060h write x d0d0h notes: 1. bus operations are defined in table 5. 2. x = any valid address within the device. ia = identifier code address: see figure 3. ba = address within the block being erased or locked. wa = address of memory location to be written. 3. srd = data read from status register. see table 8 for a description of the status register bits. wd = data to be written at location wa. data is latched on the rising edge of we# or ce# (whichever goes high first). id = data read from identifier codes. 4. following the read identifier codes command, read operations access manufacturer, device, block lock, and master lock codes. see section 6.2 for read identifier code data. 5. either 40h or 10h are recognized by the wsm as the byte write setup. 6. commands other than those shown above are reserved by intel for future device implementations and should not be used.
e ifm002/004/008a 13 preliminary 6.2 read identifier codes command the host initiates the identifier code operation by writing the read identifier codes command. following the command write, read cycles from addresses shown in figure 3 retrieve the manufacturer, device and block lock configuration codes (see table 7 for identifier code data). to terminate the operation, write another valid command. although table 7 lists the device code as either a6a6 or aaaa, this family of products could also have device code a7a7. host software should check for all three device codes listed in table 7 to achieve compatibility with both current and future cards. table 7. identifier codes code address data (2) manufacture code 00000 8989 device code 00001 2-mbyte card a6a6 4-mbyte card aaaa 8-mbyte card aaaa block lock configuration x 0002 (1) block is unlocked d 0,8 = 0 block is locked d 0,8 = 1 reserved for future use d 1-7, 9-15 notes: 1. x selects the specific block lock configuration code to be read. see figure 3 for the device identifier code memory map. 2. the addresses listed are word addresses and store 16 bits of data. see section 5.1 for more information on word addressing. 6.3 read status register command the 28f008sc or 28f016sc memory components on the series 100 miniature card each contain a status register which may be read to determine when a write, block erase, or lock bit configuration is complete, and whether that operation completed successfully (see table 8). the host may read the status register at any time by writing the read status register command to the cui. after writing this command, all subsequent read operations output data from the status register, until the host writes another valid command to the cui. the flash components latch the contents of the status register on the falling edge of oe# or ce#, whichever occurs first. oe# or ce# must be toggled to v ih before further reads to update the status register latch. note: the miniature card arranges a pair of memory devices (28f008sc devices for 2- mbyte cards and 28f016sc devices for 4- or 8-mbyte cards) in parallel to form a x16 bus. both status registers need to be checked when determining the status of a x16 erase/write operation. see section 5.1 for more information on word addressing. 6.4 clear status register command the wsm sets the erase status and write status bits to 1s and they can only be reset by the clear status register command. the wsm sets these bits to 1 when a write or erase operation has failed. the host can issue additional write and erase commands to the cui without clearing the status register. this allows a system to write a s equence of bytes before checking the write status bit. however, if an error has occurred the system will not know which write in the sequence has failed. to clear the status register, the clear status register command (5050h) is written to the cui. note: if v pp has not been turned on, the wsm sets the v pp status bit. however, the series 100 miniature card ties v pp and v cc on the 28f008sc devices together so if v cc is on then v pp will also be on. if for some reason the wsm sets the v pp status bit, the host must clear the status register before it attempts further writes or block erases. 6.5 block erase command the host executes an erase command one block at a time using a two-cycle comm and. the host writes a block erase setup command first, followed by a block erase confirm command. these two commands require appropriate sequencing and an address within the block to complete (erase changes all block data to ffh). the wsm handles block preconditioning, erase, and verify internally
ifm002/004/008a e 14 preliminary (invisible to the system). after the host writes the two-cycle block erase s equence, the device automatically outputs status register data when read. the cpu can detect block erase completion by analyzing the output data of the busy# signal or status register bit sr.7. when the block erase completes, status register bit sr.5 should be checked. if a block erase error is detected, the host should clear the status register before system software attempts corrective actions. the cui remains in read status register mode until the host issues a new command. this two-step command sequence of set-up followed by execution ensures that block contents are not accidentally erased. an invalid block erase command sequence will result in the wsm setting status register bits sr.4 and sr.5 to 1. successful block erase requires that the corresponding block lock-bit is not set. if the host attempts a block erase when the corresponding block lock-bit is set, the wsm will set sr.1 and sr.5 to 1. 6.6 word write command the host executes a word write using the provisions of the program command for 28f008sc and 28f016sc devices. the command results in a two- cycle comm and sequence. the host writes word write setup (standard 4040h or alternate 1010h) first, followed by a second write that specifies the address and data (latched on the rising edge of we#). the wsm of the written memory devices then takes over, controlling the word write and write verify algorithms internally. after the host writes the word write sequence, the device automatically outputs status register data when read. the cpu can detect the completion of the byte write event by analyzing the busy# pin or status register bit sr.7. when the wsm completes the word write, the host should check status register bit sr.4. if the host detects a write error, it should clear the status register. the internal wsm verify only detects errors for 1s that do not successfully write to 0s. the cui remains in read status register mode until it receives another command. successful word writes requires that the corresponding block lock-bit is not set. if the host attempts a write when the corresponding block lock- bit is set, the wsm will set sr.1 and sr.4 1. 6.7 block erase suspend command the block erase suspend command allows block- erase interruption to read or write data in another block of memory. once the block erase process starts, writing the block erase suspend command requests that the wsm suspend the block erase sequence at a predetermined point in the algorithm. after the host writes the block erase suspend command, the host should then write the read status register command. polling status register bits sr.7 and sr.6 can determine when the wsm suspends the block erase operation (both will be set to 1). busy# will also transition to v oh . specification t whrh2 defines the block erase suspend latency. it is also possible that the block erase completes before the device has an opportunity to suspend. the host should also check for this condition. after the block erase has been suspended, the host can issue a read array command or a word write command to any block except the one that has been suspended. using the word write suspend command (see section 6.8), a word write operation can also be suspended. during a word write operation with block erase suspended, status register bit sr.7 will return to 0 and the busy# output will transition to v ol . however, sr.6 will remain 1 to indicate block erase suspend status. the only other valid commands while block erase is suspended are read status register and block erase resume. after the host writes a block erase resume command to the flash memory, the wsm will continue the block erase process. status register bits sr.6 and sr.7 will automatically clear and busy# will return to v ol . after the host writes the erase resume command, the device automatically outputs status register data when read. block erase cannot resume until word write operations initiated during block erase suspend have completed. 6.8 word write suspend command the word write suspend command (executed at the memory device level with the 28f008sc and 28f016sc program suspend command) allows word write interruption to read data in other flash memory locations. once the word write process starts, writing the word write suspend command requests that the wsm suspend the word write sequence at a predetermined point in the algorithm.
e ifm002/004/008a 15 preliminary after the host writes the word write suspend command, it should write the read status register command. polling status register bits sr.7 and sr.2 can determine when the wsm suspends the byte write operation (both will be set to 1). busy# will also transition to v oh . specification t whrh1 defines the word write suspend latency. it is also possible that the word write completes before the device has an opportunity to suspend. the host should also check for this condition. after the word write has been suspended, the host can write the read array command to read data from any location except the suspended location. the only other valid commands while word write is suspended are read status register and word write resume. after the host writes a word write resume to the cui, the wsm will continue the word write process. the word write resume command is executed using the program resume command of the 28f008sc and 28f016sc memory devices. status register bits sr.2 and sr.7 for the commanded memory devices will automatically clear and busy# will return to v ol . after the host writes the word write resume command, the commanded memory devices automatically output status register data when read. 6.9 set block lock-bit command the host can enable a flexible block locking and unlocking scheme using the set block lock-bit command. this command enables the host to lock individual blo cks within the flash array. the block lock-bits gate program and erase operations. the host sets the block lock-bit using a two-cycle command sequence. the host writes the set block lock-bit setup command along with the appropriate block address. this command is followed by the set block lock-bit confirm command (and an address within the block to be locked). the wsm controls the set lock-bit algorithm. after the host completes the command sequence, the card automatically outputs status register data when read. the cpu can detect the completion of the set lock-bit event by analyzing the busy# pin output or status register bit sr.7. when the wsm completes the set lock-bit operation, the host should check status register bit sr.4. if the host detects an error it should clear the status register. the cui will remain in read status register mode until the host issues a new command. this two-step sequence of set-up followed by execution ensures that the host does not accidentally set the lock-bits. an invalid set block lock-bit command will result in the wsm setting status register bits sr.4 and sr.5 to 1. 6.10 clear block lock-bits command the host clears all set block lock-bits in parallel using the clear block lock-bits command. the host is free to clear block lock-bits using the clear block lock-bits command the host executes the clear block lock-bits operation using a two- cycle comm and sequence. the host must first issue a clear block lock-bits set-up command. this command is followed by a confirm command. after the host completes the two-cycle comm and sequence, the device automatically outputs status register data when read. the cpu can detect completion of the clear block lock-bits event by analyzing the busy# pin output or status register bit sr.7. when the wsm completes the operation, the host should check status register bit sr.5. if the host detects a clear block lock-bit error, the host should clear the status register. the cui will remain in read status register mode until the host issues another command. this two-step sequence of set-up followed by execution ensures that the host does not accidentally clear block lock-bits. an invalid clear block lock-bits command sequence will result in the wsm setting status register bits sr.4 and sr.5 to 1. if a clear block lock-bits operation is aborted due to v cc transitioning out of valid range or reset# active transition, block lock-bit values are left in an undetermined state. the host must repeat the clear block lock-bits command to initialize block lock-bit contents to known values.
ifm002/004/008a e 16 preliminary table 8. status register definition wsms ess eclbs bwslbs vpps bwss dps r 76543210 sr.7 = write state machine status 1 = ready 0 = busy sr.6 = erase suspend status 1 = block erase suspended 0 = block erase in progress/completed sr.5 = erase and clear lock-bits status 1 = error in block erasure or clear lock-bits 0 = successful block erase or clear lock-bits sr.4 = byte write and set lock-bit status 1 = error in byte write or set master/block lock-bit 0 = successful byte write or set master/block lock bit sr.3 = v pp status 1 = v pp low detect, operation abort 0 = v pp ok sr.2 = byte write suspend status 1 = byte write suspended 0 = byte write in progress/completed sr.1 = device protect status 1 = block lock-bit and/or reset# lock detected, operation abort 0 = unlock sr.0 = reserved for future enhancements notes: check busy# or sr.7 to determine block erase, byte write, or lock-bit configuration completion. sr.6-0 are invalid while sr.7 = 0. if both sr.5 and sr.4 are 1s after a block erase or lock-bit configuration attempt, an improper command sequence was entered. sr.3 indicates the v pp status. however, the miniature card internally ties v pp to v cc so this bit should not be set to 1. if for some reason this bit is set, the host should write the clear status register command. sr.1 does not provide a continuous indication of master and block lock-bit values. the wsm interrogates the master lock-bit, block lock-bit, and reset# only after block erase, byte write, or lock-bit configuration command sequences. it informs the system, depending on the attempted operation, if the block lock-bit is set, master lock-bit is set, and/or reset# is not v hh . reading the block lock and master lock configuration codes after writing the read identifier codes command indicates master and block lock-bit status. sr.0 is reserved for future use and should be masked out when polling the status register. 7.0 card attribute information the card attribute information consists of the miniature cards attribute information structure (ais) as well as the pc cards card information structure (cis). these two structures co-exist for compatibility with both industry standards. this allows the series 100 miniature card to function in both pc card and miniature card environments. the card attribute information data for the series 100 miniature card is found in section 7.3. for more information on the description of these structures refer to the appropriate specification. caution: the card attribute information data is located in block 0. this information is not write protected and should not be erased by the system software if this information is needed for card recognition.
e ifm002/004/008a 17 preliminary 7.1 card information structure the cis begins at address 0000h (device tuple) of the cards memory. the cis data resides only in the low byte of the word. it contains a variable length chain of data blocks (tuples) that conform to a basic format. see table 9 for the cis memory map. 7.2 attribute information structure the ais begins at address 0010h (identifier byte) of the cards memory. the ais data resides only in the low byte of the word. it contains a fixed list of data information that ends at address 00ffh. see table 10 for the ais memory map. note: all addresses listed in table 9 and 10 are word addresses. table 9. cis memory map tuple name description tuple code address location cistpl_device device information 01h 0h - 04h cistpl_null null (ignore) 00h 05h - 0dh cistpl_mini miniature card ais (vendor unique) 80h 0eh - ffh cistpl_devicegeo device geometry information 1eh 100h - 107h cistpl_manfid manufacturer identification string 20h 108h - 10dh cistpl_funcid function class identification 21h 10eh - 111h cistpl_longlink_c longlink to common memory 12h 112h - 117h cistpl_vers_1 level 1 version/product information 15h 118h - 167h cistpl_device_oc other operating conditions device info. 1ch 168h - 16ch cistpl_jedec_c jedec id 18h 16dh - 170h cistpl_end the end-of-chain tuple ffh 171h - 172h table 10. ais memory map ais section description address location identification data identifies card type 10h - 3fh compatibility data describes attributes of card 40h - 4fh not used reserved for future use 50h - ffh
ifm002/004/008a e 18 preliminary 7.3 card attribute information data address values description 00h 01h cistpl_device 01h 03h tpl_link 02h 54h flash = 100 ns 03h 06h card size: 2 mb 0eh card size: 4 mb 1eh card size 8mb 04h ffh end of device 05h - 0dh 00h null 0eh 80h cistpl_min 0fh f0h tpl_link 10h 99h identifier 11h 10h rev 1.0 compliant 12h ffh 2-mb ais checksum f9h 4-mb ais checksum f4h 8-mb ais checksum 13h 49h manufacturer name i 14h 4eh n 15h 54h t 16h 45h e 17h 4ch l 18h 20h space 19h 43h c 1ah 4fh o 1bh 52h r 1ch 50h p 1dh 4fh o 1eh 52h r 1fh 41h a 20h 54h t address values description 21h 49h i 22h 4fh o 23h 4eh n 24h - 26h 00h null 27h 53h card name s 28h 45h e 29h 52h r 2ah 49h i 2bh 45h e 2ch 53h s 2dh 20h space 2eh 31h 1 2fh 30h 0 30h 30h 0 31h 20h space 32h 43h c 33h 41h a 34h 52h r 35h 44h d 36h - 3ah 00h null 3bh 01h 1 technology device 3ch - 3fh 00h reserved space set to 00h 40h 00h flash 41h 89h device jedec manufacturer id 42h a6h 2-mb device component jedec id aah 4-mb device component jedec id aah 8-mb device component jedec id
e ifm002/004/008a 19 preliminary address values description 43h 01h 2 mb 03h 4 mb 07h 8 mb 44h 00h no x.x v accesses 45h 0fh 150 ns 3.3 v access time 46h 0ah 100 ns 5.0 v access time 47h 00h no x.x v accesses 48h 25h 20 ma read/50 ma write @ 3.3 v 49h 46h 40 ma read/60 ma write @ 5.0 v 4ah 01h 100 m a standby - 2 mb 01h 100 m a standby - 4 mb 01h 200 m a standby - 8 mb 4bh - 4fh 00h reserved 50 - ff 00h null / not used 100h 1eh cistpl_devicegeo 101h 06h tpl_link 102h 02h dgtpl_bus 103h 11h dgtpl_ebs 104h 01h dgtpl_rbs 105h 01h dgtpl_wbs 106h 03h dgtpl_part = 1 107h 01h flash device interleave 108h 20h cistpl_manfid 109h 04h tpl_link 10ah 89h tplmid_manf: lsb (intel jedec id) 10bh 00h tplmid_manf: msb 10ch 03h 2 mb - 100 ns address values description 13h 4 mb - 100 ns 23h 8 mb - 100 ns 02h 2 mb - 150 ns 12h 4 mb - 150 ns 22h 8 mb - 150 ns 10dh 85h tplmid_card msb 10eh 21h cistpl_funcid 10fh 02h tpl_link 110h 01h tplfid_function : memory 111h 00h tplfid_sysinit 112h 12h cistpl_longlink_c 113h 04h tpl_link 114h 00h lowest byte 115h 00h mid byte 116h 02h mid byte 117h 00h highest byte 118h 15h cistpl_vers1 119h 4eh tpl_link 11ah 05h tpllv1_major 11bh 00h tpllv1_minor 11ch 49h tpllv1_info i 11dh 6eh n 11eh 74h t 11fh 65h e 120h 6ch l 121h 00h end text 122h 53h s 123h 45h e 124h 52h r
ifm002/004/008a e 20 preliminary address values description 125h 49h i 126h 45h e 127h 53h s 128h 20h space 129h 31h 1 12ah 30h 0 12bh 30h 0 12ch 20h space 12dh 46h f 12eh 4ch l 12fh 41h a 130h 53h s 131h 48h h 132h 20h space 133h 4dh m 134h 49h i 135h 4eh n 136h 49h i 137h 41h a 138h 54h t 139h 55h u 13ah 52h r 13bh 45h e 13ch 20h space 13dh 43h c 13eh 41h a 13fh 52h r 140h 44h d 141h 00h end text address values description 142h 30h 2 mb 30h 4 mb 30h 8 mb 143h 32h 2 mb 34h 4 mb 38h 8 mb 144h 20h space 145h 00h end text 146h 43h c 147h 4fh o 148h 50h p 149h 59h y 14ah 52h r 14bh 49h i 14ch 47h g 14dh 48h h 14eh 54h t 14fh 20h space 150h 49h i 151h 4eh n 152h 54h t 153h 45h e 154h 4ch l 155h 20h space 156h 43h c 157h 4fh o 158h 52h r 159h 50h p 15ah 4fh o
e ifm002/004/008a 21 preliminary address values description 15bh 52h r 15ch 41h a 15dh 54h t 15eh 49h i 15fh 4fh o 160h 4eh n 161h 20h space 162h 31h 1 163h 39h 9 164h 39h 9 165h 36h 6 166h 00h end text 167h ffh end of list 168h 1ch cistpl_device_oc 169h 03h tpl_link 16ah 02h 3.3v operation 16bh 53h 150 ns access time 16ch 06h card size: 2 mb 0eh card size: 4 mb 1eh card size 8 mb 16dh 18h cistpl_jedec_c 16eh 02h tpl_link 16fh 89h manufacturer id 170h a6h 2 mb device component jedec id aah 4 mb device component jedec id aah 8 mb device component jedec id 171eh ffh cistpl_end 172fh 00h invalid address 8.0 system design considerations 8.1 power supply decoupling flash memory power-switching characteristics require careful device decoupling. system designers are interested in three supply current issues: standby, active and transient current peaks which are produced by rising and falling edges of cel# and ceh#. the capacitive and inductive loads on the card and internal flash memory device pairs determine the magnitudes of these peaks. the host system s hould also have a 4.7 f electrolytic capacitor between v cc and gnd as close to the connector as possible. the bulk capacitance overcome voltage slumps caused by printed-circuit-board trace inductance, and supply charge to the smaller capacitors as needed. 8.2 power-up/down protection the miniature card specified socket properly sequences the power supplies to the flash memory card via power/insertion signals that connect before the interface signals. each device in the memory card is designed to offer protection against accidental erasure or writing, caused by spurious system-level si gnals that may exist during power transitions. the card will power-up into the read state. a system desi gner must guard against active writes for v cc voltages above v lko (2.0 v). since we# and ceh#/cel# must be active for a command write, driving either to v ih will inhibit writes. the card provides 100 k w pull-up resistors on ceh# and cel# to provide some protection against spurious writes. the two-step command sequence for a write provides additional protection against accidental writes to the card.
ifm002/004/008a e 22 preliminary 8.3 busy# and byte write/block erase polling busy# is a cmos output that provides a hardware method of detecting byte write and block erase completion. busy# transitions low a maximum of 100 ns after the host issues a write or erase command sequence. busy# returns to v oh when the wsm has finished executing the internal algorithm or the host suspends the current operation. busy# can be connected to the interrupt input of the system cpu or controller. it is active at all times. busy# is also v oh when the device is in erase suspend or deep power-down modes. 8.4 v cc , reset# transitions and the command/status registers reset# transitions to v il during write and block erase also aborts the operations. data is partially altered in either case, and the command sequence must be repeated after normal operation is restored. device power-off, or reset# transitioning to v il , clears the status register of the cards memory devices to initial value 100000xx. systems that do not support reset# or power- down functionality must tie the reset# signal to v cc . the cui latches commands issued by system software and is not altered by ce# transitions or wsm actions. the cui defaults to read array mode upon power-up, exit from deep power-down, or after v cc transitions below v lko . after write or block erase is complete, the cui must be reset to read array mode via the read array command, if access to the memory array is desired. 8.5 preformatted for ftl ftl is an industry-standard file format for storing data in flash memory. in order for ftl host software to read and write data files to the miniature card, the card must first be formatted for ftl. formatting includes adding ftl structures on every block boundary of the flash array. all miniature cards come pre-programmed with appropriate ftl structures on the card.
e ifm002/004/008a 23 preliminary 9.0 electrical specifications 9.1 absolute maximum ratings* commercial operating temperature during read, block erase, word write, and lock-bit configuration ...... 0 c to +60 c (1) temperature under bias......... C10 c to +70 c storage temperature ................... C30 c to +70 c voltage on any pin.....................C2.0 v to +7.0 v (2) output short circuit current .................... 100 ma (3) notice: this datasheet contains preliminary information on products in production. do not finalize a design with this information. revised information will be published when the product is available. verify with your local intel sales office that you have the latest datasheet before finalizing a design * warning: stressing the device beyond the "absolute maximum ratings" may cause permanent damage. these are stress ratings only. operation beyond the "operating conditions" is not recommended and extended exposure beyond the "operating conditions" may effect device reliability. notes: 1. operating temperature is for commercial product defined by this specification. 2. all specified voltages are with respect to gnd. minimum dc voltage is C0.5 v on input/output pins and C0.2 v on v cc . during transitions, this level may undershoot to C2.0 v for periods <20 ns. maximum dc voltage on input/output signals is v cc +0.5 v which, during transitions, may overshoot to v cc +2.0 v for periods <20 ns. 3. output shorted for no more than one second. no more than one output shorted at a time. 9.2 operating conditions symbol parameter notes min max unit test condition t a operating temperature 0 +60 c ambient temperature v cc1 v cc supply voltage (3.3 v 0.3 v) 3.0 3.6 v v cc2 v cc supply voltage (5 v 5%) 4.75 5.25 v 9.3 capacitance (1) symbol parameter typical maximum unit condition c in input capacitance 24 32 pf v in = 0.0 v c out output capacitance 16 24 pf v out = 0.0 v notes: 1. sampled, not 100% tested.
ifm002/004/008a e 24 preliminary 9.4 dc characteristics (6) v cc = 3.3 v v cc = 5 v test sym parameter notes typ max typ max unit conditions i li input load current 1,4 20 20 m a v cc = v cc max, v in = v cc or gnd i lo output leakage current 12020 m a v cc = v cc max, v in = v cc or gnd i ccs v cc standby current m a v cc = v cc max 2-mbyte card 1,3 48 250 58 250 cel# = ceh# = reset# = 4-mbyte card 1,3 48 250 58 250 v cc 0.2 v 8-mbyte card 1,3 108 560 128 560 i ccd v cc deep power-down current m a reset# = gnd 0.2 v 2-mbyte card 1,3 50 50 i out (ry/by#) = 0 ma 4-mbyte card 1,3 50 50 8-mbyte card 1,3 160 160 i ccr v cc read current 1,3,5 20 25 35 70 ma v cc = v cc max, cel#/ceh# = gnd, f = 5 mhz (3.3 v), f = 8 mhz (5.0 v), i out = 0 ma i ccw v cc word write or set lock-bit current 1,4 45 115 60 150 ma i cce v cc block erase or clear lock-bit current 1,4 45 75 60 100 ma i ccws i cces v cc word write or block erase suspend current 1,2 6 12 10 20 ma cel# = ceh# = v ih notes: 1. all currents are in rms unless otherwise noted. these currents are valid for all product versions (packages and speeds). contact intels application support hotline or your local sales office for information about typical specifications. 2. i ccws and i cces are specified with the device de-selected. if read or byte written while in erase suspend mode, the devices current draw is the sum of i ccws or i cces and i ccr or i ccw , respectively. 3. cmos inputs are either v cc 0.2 v or gnd 0.2 v. 4. exceptions: with v in = gnd, the leakage current on cel#, ceh# will be <50 m a each due to internal pull-up resistors. 5. automatic power savings (aps) reduces typical i ccr to 2 ma at 5 v v cc and 6 ma at 3.3 v v cc in static operation (addresses not switching). 6. all values are based on word accesses. values for byte accesses are 50% of the specification listed.
e ifm002/004/008a 25 preliminary 9.4 dc characteristics (continued) v cc = 3.3 v v cc = 5 v test sym parameter notes min max min max unit conditions v il input low voltage C0.5 0.8 C0.5 0.8 v v ih input high voltage 0.7 v cc v cc + 0.5 2.0 v cc + 0.5 v v ol output low voltage 0.1 v cc 0.1 v cc v v cc = v cc min i ol = 4.0 ma at 5 v i ol = 2 ma at 3.3 v v oh output high voltage 0.9 v cc 0.9 v cc v v cc = v cc min i oh = C1 ma v lko v cc lockout voltage 2.0 2.0 v test points input output 1.5 3.0 0.0 1.5 0581_06 note: 1. ac test inputs are driven at 3.0 v for a logic 1 and 0.0 v for a logic 0. input timing begins, and output timing ends, at 1.5 v. input rise and fall times (10% to 90%) < 10 ns. figure 5. transient input/output reference waveform for v cc = 3.3 v 0.3 v and v cc = 5 v 5% (standard testing configuration)
ifm002/004/008a e 26 preliminary 9.5 ac characteristics ac timing diagrams and characteristics are guaranteed to meet or exceed the miniature card specification. 9.5.1 read operations parameter ieee symbol 5 v min 5 v max 3.3 v min 3.3 v max unit read cycle time t avav 100 150 ns address access time t avqv 100 150 ns ce# access time t elqv 100 150 ns oe# access time t glqv 50 50 ns output disable time from oe# inactive t ghqz 10 20 ns output enable time from oe# active (1) t glqnz 55ns output enable time from ce# active (1) t elqnz 55ns data hold from address, ce#, or oe# change (whichever occurs first) t axqx 00ns ce# setup time to oe# active t elgl 00ns address setup time to oe# active t avgl 00ns reset# high to output delay t phqv 400 600 ns notes: 1. sampled, not 100% tested. t t t t t t t t t t t t note 1 note 1 data valid a[25:0] cel#/ceh# oe# d[15:0] avav avqv avgl elgl elqnz elqv glqv glqnz ghqz ghqx ehqx axqx 0581_09 note: 1. shaded region may be high or low. figure 6. ac waveforms for read operations
e ifm002/004/008a 27 preliminary 9.5.2 write operations parameter ieee symbol 5 v min 5 v max 3.3 v min 3.3 v max unit write cycle time t avav 100 150 ns address access time t avqv 100 150 ns ce# access time t elqv 100 150 ns we# pulse width t wlwh 40 50 ns address setup time to we# active t avwl 00ns data setup time to we# inactive t dvwh 40 50 ns data hold time from we# inactive t whdx 55ns address hold time from we# inactive t whax 55ns ce# hold time from we# inactive t wheh 10 10 ns reset# high to we# active t phwl 11 m s t t t t t t t note 1 note 1 a[25:0] cel#/ceh# we# d[15:0] avav avwl whax wheh dvwh wlwh whdx 0581_10 note: 1. shaded region may be high or low. figure 7. ac waveforms for write operations
ifm002/004/008a e 28 preliminary 9.5.3 power-up timing symbol parameter notes min max units t su (cel#/ceh#) ce# setup time 1 ms t su (reset#) reset# setup time 1 ms t pr v cc rising time 1 0.1 100 ms t w (reset#) reset# width 1 s note: 1. the t pr is defined as a linear waveform in the period of 10% to 90%. even if the waveform is not a linear waveform, its rising time must meet this specification. v 2v cel#/ceh# hi-z t (cel#/ceh#) t (reset#) t t (reset#) reset# v @ 10% v cc v @ 90% cc ih cc su su w t (reset#) su t (reset#) w pr 0581_11 figure 8. power-up timing for systems supporting reset#
e ifm002/004/008a 29 preliminary 9.6 erase and data write performance (3, 4, 5) v cc = 3.3 v v cc = 5.0 v sym parameter notes min typ (1) max min typ (1) max unit t whqv1 t ehqv1 word write time 2 17 8 s block write time 2 1.1 0.5 sec t whqv2 t ehqv2 block erase time 2 1.8 1.1 sec t whqv3 t ehqv3 set lock-bit time 2 21 12 s t whqv4 t ehqv4 clear block lock-bits time 2 1.8 1.1 sec t whrh1 t ehrh1 word write suspend latency time to read 67 56s t whrh2 t ehrh2 erase suspend latency time to read 16.2 20 9.6 12 s notes: 1. typical values measured at t a = +25 c and nominal voltages. assumes corresponding lock-bits are not set. subject to change based on device characterization. 2. excludes system-level overhead. 3. these performance numbers are valid for all speed versions. 4. sampled but not 100% tested. 5. the maximum word/byte write time is the absolute maximum time it takes the write algorithm to complete. the over- whelming majority of the bits program in the typical value specified.
ifm002/004/008a e 30 preliminary 10.0 packaging figure 9 shows the outside dimensions of the series 100 miniature card. for complete mechanical drawings refer to the miniature card specification. 3.5 mm 33 mm 38 mm 3.3v / 5v key x alignment notch latching notches y alignment notches 0581_12 note: for complete dimensions of the 3.3v/5.0 v key, to the miniature card specification. figure 9. miniature card dimensions
e ifm002/004/008a 31 preliminary 11.0 ordering information ifm004a, shxxxxx where: i = intel fm = flash miniature card 004 = density in megabytes (002, 004, 008 available) a = revision shxxxxx = customer identifier 12.0 additional information related intel information (1,2) order number document 290597 5 volt flashfile? memory family; 28f004s5, 28f008s5, 28f016s5 datasheet (see note 3) 290598 3 volt flashfile? memory family; 28f004s3, 28f008s3, 28f016s3 datasheet (see note 4) 297717 series 100 flash memory miniature card specification update notes: 1. please call the intel literature center at (800) 548-4725 to request intel documentation. international customers should contact their local intel or distribution sales office. 2. visit intels world wide web home page at http://www.intel.com for technical documentation and tools. 3. the indicated datasheet describes the characteristics and operation of the cards memory devices for 5 v v cc . 4. the indicated datasheet describes the characteristics and operation of the cards memory devices for 3 v v cc .

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